module regfile_wrapper(
  input          clk,
  input  [  4:0] mode,
  input  [ 16:0] read_in_bundle,
  output [127:0] read_out_bundle,
  input  [ 80:0] write_in_bundle
);

wire [3:0] rn_sel;
wire [3:0] rm_sel;
wire [3:0] rs_sel;
wire [3:0] rd_sel;
wire       rd_sel_usr;

wire [31:0] rn;
wire [31:0] rm;
wire [31:0] rs;
wire [31:0] rd;

wire        we0;
wire [ 3:0] wa0;
wire [31:0] d0;
wire        we1;
wire [ 3:0] wa1;
wire [31:0] d1;
wire        wa0_exc;
wire [ 4:0] wa0_mode_exc;
wire        wa1_usr;

assign {rn_sel, rm_sel, rs_sel, rd_sel, rd_sel_usr} = read_in_bundle;
assign read_out_bundle = {rn, rm, rs, rd};
assign {we0, wa0, wa0_exc, wa0_mode_exc, d0, we1, wa1, wa1_usr, d1} = write_in_bundle;

regfile u_regfile(
  .i_clk(clk),
  .i_mode(mode),
  .i_rn_sel(rn_sel),
  .i_rm_sel(rm_sel),
  .i_rs_sel(rs_sel),
  .i_rd_sel(rd_sel),
  .i_rd_sel_usr(rd_sel_usr),
  .o_rn(rn),
  .o_rm(rm),
  .o_rs(rs),
  .o_rd(rd),
  .i_we0(we0),
  .i_wa0(wa0),
  .i_d0(d0),
  .i_we1(we1),
  .i_wa1(wa1),
  .i_d1(d1),
  .i_wa0_exc(wa0_exc),
  .i_wa0_mode_exc(wa0_mode_exc),
  .i_wa1_usr(wa1_usr)
);

endmodule
